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EL5123, EL5223, EL5323, EL5423
Data Sheet November 19, 2004 FN7176.1
12MHz 4, 8, 10 & 12 Channel Rail-to-Rail Input-Output Buffers
The EL5123, EL5223, EL5323, and EL5423 are low power, high voltage rail-to-rail input/output buffers designed primarily for use in reference voltage buffering applications for TFT-LCDs. They are available in quad (EL5123), octal (EL5223), 10-channel (EL5323), and 12-channel (EL5423) topologies. All buffers feature a -3dB bandwidth of 12MHz and operate from just 600A per buffer. This family also features fast slewing and settling times, as well as a continuous output drive capability of 30mA (sink and source). The quad channel EL5123 is available in the 10-pin MSOP package. The 8-channel EL5223 is available in both the 20pin TSSOP and 24-pin QFN packages, the 10-channel EL5323 in the 24-pin TSSOP and 24-pin QFN packages, and the 12-channel EL5423 in the 28-pin TSSOP and 32-pin QFN packages. All buffers are specified for operation over the full -40C to +85C temperature range.
Features
* 12MHz -3dB bandwidth * Supply voltage = 4.5V to 16.5V * Low supply current (per buffer) = 600A * High slew rate = 15V/s * Rail-to-rail input/output swing * Ultra-small packages * Pb-free available (RoHS compliant)
Applications
* TFT-LCD drive circuits * Electronics notebooks * Electronic games * Touch-screen displays * Personal communication devices * Personal digital assistants (PDA) * Portable instrumentation * Sampling ADC amplifiers * Wireless LANs * Office automation * Active filters * ADC/DAC buffers
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002-2004. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners.
EL5123, EL5223, EL5323, EL5423 Pinouts
EL5223 & EL5323 (24-PIN QFN) TOP VIEW
21 VOUT1* 20 VOUT2 23 VIN1* 24 VIN2
EL5123 (10-PIN MSOP) TOP VIEW
VIN1 1 VIN2 2 19 VOUT3 18 VOUT4 17 VOUT5 VS+ 3 VIN3 4 VIN4 5 10 VOUT1 9 VOUT2 8 VS7 VOUT3 6 VOUT4
EL5223 (20-PIN TSSOP) TOP VIEW
VIN1 1 VIN2 2 VIN3 3 VIN4 4 VS+ 5 VS+ 6 VIN5 7 VIN6 8 VIN7 9 VIN8 10 20 VOUT1 19 VOUT2 18 VOUT3 17 VOUT4 16 VS15 VS14 VOUT5 13 VOUT6 12 VOUT7 11 VOUT8
VIN3 1 VIN4 2 VIN5 3 VS+ 4 VIN6 5 VIN7 6 VIN8 7 NC 10 VOUT10* 11 CVIN10* 9 VOUT9 12 VIN9 8 THERMAL PAD
22 NC
16 VS15 VOUT6 14 VOUT7 13 VOUT8
* NOT AVAILABLE IN EL5223
EL5423 (32-PIN QFN) TOP VIEW
27 VOUT1 26 VOUT2 32 VIN2 31 VIN1
EL5423 (28-PIN TSSOP) TOP VIEW
VIN1 1 VIN2 2 25 VOUT3 24 VOUT4 23 VOUT5 22 VOUT6 VIN3 3 VIN4 4 VIN5 5 VIN6 6 VS+ 7 VS+ 8 VIN7 9 VIN8 10 VIN9 11 VIN10 12 VIN11 13 VIN12 14 28 VOUT1 27 VOUT2 26 VOUT3 25 VOUT4 24 VOUT5 23 VOUT6 22 VS21 VS20 VOUT7 19 VOUT8 18 VOUT9 17 VOUT10 16 VOUT11 15 VOUT12
EL5323 (24-PIN TSSOP) TOP VIEW
VIN1 1 VIN2 2 VIN3 3 VIN4 4 VIN5 5 VS+ 6 VS+ 7 VIN6 8 VIN7 9 VIN8 10 VIN9 11 VIN10 12 24 VOUT1 23 VOUT2 22 VOUT3 21 VOUT4 20 VOUT5 19 VS18 VS17 VOUT6 16 VOUT7 15 VOUT8 14 VOUT9 13 VOUT10
30 NC
29 NC
VIN3 1 VIN4 2 VIN5 3 VIN6 4 VS+ 5 VIN7 6 VIN8 7 VIN9 8 VIN10 9 VIN11 10 VIN12 11 NC 12 NC 13 NC 14 VOUT12 15 VOUT11 16 THERMAL PAD
28 NC
21 VS20 VOUT7 19 VOUT8 18 VOUT9 17 VOUT10
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FN7176.1 November 19, 2004
EL5123, EL5223, EL5323, EL5423 Ordering Information
PART NO. EL5123CY EL5123CY-T7 EL5123CY-T13 EL5123CYZ (See Note) EL5123CYZ-T7 (See Note) EL5123CYZ-T13 (See Note) EL5223CL EL5223CL-T7 EL5223CL-T13 EL5223CLZ (See Note) EL5223CLZ-T7 (See Note) EL5223CLZ-T13 (See Note) EL5223CR EL5223CR-T7 EL5223CR-T13 EL5223CRZ (See Note) EL5223CRZ-T7 (See Note) EL5223CRZ-T13 (See Note) EL5323CL EL5323CL-T7 EL5323CL-T13 PACKAGE 10-Pin MSOP 10-Pin MSOP 10-Pin MSOP 10-Pin MSOP (Pb-Free) 10-Pin MSOP (Pb-Free) 10-Pin MSOP (Pb-Free) 24-Pin QFN 24-Pin QFN 24-Pin QFN 24-Pin QFN (Pb-Free) 24-Pin QFN (Pb-Free) 24-Pin QFN (Pb-Free) 20-Pin TSSOP 20-Pin TSSOP 20-Pin TSSOP 20-Pin TSSOP (Pb-Free) 20-Pin TSSOP (Pb-Free) 20-Pin TSSOP (Pb-Free) 24-Pin QFN 24-Pin QFN 24-Pin QFN TAPE & REEL 7" 13" 7" 13" 7" 13" 7" 13" 7" 13" 7" 13" 7" 13" PKG. DWG. # MDP0043 MDP0043 MDP0043 MDP0043 MDP0043 MDP0043 MDP0046 MDP0046 MDP0046 MDP0046 MDP0046 MDP0046 MDP0044 MDP0044 MDP0044 MDP0044 MDP0044 MDP0044 MDP0046 MDP0046 MDP0046 PART NO. EL5323CLZ (See Note) EL5323CLZ-T7 (See Note) EL5323CLZ-T13 (See Note) EL5323CR EL5323CR-T7 EL5323CR-T13 EL5323CRZ (See Note) EL5323CRZ-T7 (See Note) EL5323CRZ-T13 (See Note) EL5423CL EL5423CL-T7 EL5423CL-T13 EL5423CLZ (See Note) EL5423CLZ-T7 (See Note) EL5423CLZ-T13 (See Note) EL5423CR EL5423CR-T7 EL5423CR-T13 EL5423CRZ (See Note) EL5423CRZ-T7 (See Note) EL5423CRZ-T13 (See Note) PACKAGE 24-Pin QFN (Pb-Free) 24-Pin QFN (Pb-Free) 24-Pin QFN (Pb-Free) 24-Pin TSSOP 24-Pin TSSOP 24-Pin TSSOP 24-Pin TSSOP (Pb-Free) 24-Pin TSSOP (Pb-Free) 24-Pin TSSOP (Pb-Free) 32-Pin QFN 32-Pin QFN 32-Pin QFN 32-Pin QFN (Pb-Free) 32-Pin QFN (Pb-Free) 32-Pin QFN (Pb-Free) 28-Pin TSSOP 28-Pin TSSOP 28-Pin TSSOP 28-Pin TSSOP (Pb-Free) 28-Pin TSSOP (Pb-Free) 28-Pin TSSOP (Pb-Free) TAPE & REEL 7" 13" 7" 13" 7" 13" 7" 13" 7" 13" 7" 13" 7" 13" PKG. DWG. # MDP0046 MDP0046 MDP0046 MDP0044 MDP0044 MDP0044 MDP0044 MDP0044 MDP0044 MDP0046 MDP0046 MDP0046 MDP0046 MDP0046 MDP0046 MDP0044 MDP0044 MDP0044 MDP0044 MDP0044 MDP0044
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pbfree peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
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FN7176.1 November 19, 2004
EL5123, EL5223, EL5323, EL5423
Absolute Maximum Ratings (TA = 25C)
Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . .+18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.5V, VS +0.5V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves ESD Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER INPUT CHARACTERISTICS VOS TCVOS IB RIN CIN AV
VS+ = +5V, VS- = -5V, RL = 10k and CL = 10pF to 0V, TA = 25C unless otherwise specified. CONDITION MIN TYP MAX UNIT
DESCRIPTION
Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Impedance Input Capacitance Voltage Gain
VCM = 0V (Note 1) VCM = 0V
0.5 5 2 1 1.35
12
mV V/C
50
nA G pF
-4.5V VOUT 4.5V
0.99
1.01
V/V
OUTPUT CHARACTERISTICS VOL VOH IOUT (max) Output Swing Low Output Swing High Output Current (Note 2) IL = -5mA IL = +5mA RL = 10 4.85 -4.95 4.95 120 -4.85 V V mA
POWER SUPPLY PERFORMANCE PSRR IS Power Supply Rejection Ratio Supply Current VS is moved from 2.25V to 7.75V No load (EL5123) No load (EL5223) No load (EL5323) No load (EL5423) DYNAMIC PERFORMANCE SR tS BW CS NOTES: 1. Measured over operating temperature range. 2. Instantaneous peak current. 3. Slew rate is measured on rising and falling edges. Slew Rate (Note 3) Settling to +0.1% (AV = +1) -3dB Bandwidth Channel Separation -4.0V VOUT 4.0V, 20% to 80% (AV = +1), VO = 2V step RL = 10k, CL = 10pF f = 5MHz 7 15 250 12 75 V/s ns MHz dB 55 80 2.4 5.5 6 7.45 3.4 6.8 8.5 10.1 dB mA mA mA mA
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FN7176.1 November 19, 2004
EL5123, EL5223, EL5323, EL5423
Electrical Specifications
PARAMETER INPUT CHARACTERISTICS VOS TCVOS IB RIN CIN AV Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Impedance Input Capacitance Voltage Gain 0.5V VOUT 4.5V 0.99 VCM = 2.5V (Note 1) VCM = 2.5V 0.5 5 2 1 1.35 1.01 50 12 mV V/C nA G pF V/V VS+ =+5V, VS- = 0V, RL = 10k and CL = 10pF to 2.5V, TA = 25C unless otherwise specified. CONDITION MIN TYP MAX UNIT
DESCRIPTION
OUTPUT CHARACTERISTICS VOL VOH IOUT (max) Output Swing Low Output Swing High Output Current (Note 2) IL = -2.5mA IL = +2.5mA RL = 10 4.85 80 4.92 120 150 mV V mA
POWER SUPPLY PERFORMANCE PSRR IS Power Supply Rejection Ratio Supply Current VS is moved from 4.5V to 15.5V No load (EL5123) No load (EL5223) No load (EL5323) No load (EL5423) DYNAMIC PERFORMANCE SR tS BW CS NOTES: 1. Measured over operating temperature range. 2. Instantaneous peak current. 3. Slew rate is measured on rising and falling edges Slew Rate (Note 3) Settling to +0.1% (AV = +1) -3dB Bandwidth Channel Separation 1V VOUT 4V, 20% to 80% (AV = +1), VO = 2V step RL = 10k, CL = 10pF f = 5MHz 12 250 12 75 V/s ns MHz dB 55 80 2.4 5.2 5.8 7.2 3.2 6.5 8 9.7 dB mA mA mA mA
5
FN7176.1 November 19, 2004
EL5123, EL5223, EL5323, EL5423
Electrical Specifications
PARAMETER INPUT CHARACTERISTICS VOS TCVOS IB RIN CIN AV Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Impedance Input Capacitance Voltage Gain 0.5V VOUT 14.5V 0.99 VCM = 7.5V (Note 1) VCM = 7.5V 0.5 5 2 1 1.35 1.01 50 14 mV V/C nA G pF V/V VS+ = +15V, VS- = 0V, RL = 10k and CL = 10pF to 7.5V, TA = 25C unless otherwise specified. CONDITION MIN TYP MAX UNIT
DESCRIPTION
OUTPUT CHARACTERISTICS VOL VOH IOUT (max) Output Swing Low Output Swing High Output Current (Note 2) IL = -7.5mA IL = +7.5mA RL = 10 14.85 120 80 14.95 200 150 mV V mA
POWER SUPPLY PERFORMANCE PSRR IS Power Supply Rejection Ratio Supply Current VS is moved from 4.5V to 15.5V No load (EL5123) No load (EL5223) No load (EL5323) No load (EL5423) DYNAMIC PERFORMANCE SR tS BW CS NOTES: 1. Measured over operating temperature range. 2. Instantaneous peak current. 3. Slew rate is measured on rising and falling edges. Slew Rate (Note 3) Settling to +0.1% (AV = +1) -3dB Bandwidth Channel Separation 1V VOUT 14V, 20% to 80% (AV = +1), VO = 2V step RL = 10k, CL = 10pF f = 5MHz 18 250 12 75 V/s ns MHz dB 55 80 2.4 5.7 6.2 7.8 3.7 7.1 8.7 10.4 dB mA mA mA mA
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FN7176.1 November 19, 2004
EL5123, EL5223, EL5323, EL5423 Typical Performance Curves
12 10 8 VOP-P (V) 6 4 2 THD + NOISE (%) VS=5V RL=10k 100K 1M 10M 0.018 VS=5V RL=10k 0.016 V =2V IN P-P 0.014 0.012 0.01 0.008 0.006 1K
0 10K
10K FREQUENCY (Hz)
100K
FREQUENCY (Hz)
FIGURE 1. OUTPUT SWING vs FREQUENCY
FIGURE 2. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY
10
80
OVERSHOOT (%)
VS=5V 70 RL=10k VIN=100mV 60 50 40 30 20 10 0 10 100 CAPACITANCE (pF) 1K STEP SIZE (V)
VS=5V RL=10k 6 CL=12pF
2
-2
-6
-10 200 250 300 350 400 450 500 550 600 650 SETTLING TIME (ns)
FIGURE 3. OVERSHOOT vs LOAD CAPACITANCE
20 NORMALIZED MAGNITUDE (dB)
FIGURE 4. SETTLING TIME vs STEP SIZE
20
10
100pF
NORMALIZED MAGNITUDE (dB)
VS=5V RL=10k
1000pF
VS=5V CL=10pF 1k
10 0 562 -10 -20 -30 100K 150 10k
0 47pF -10 12pF
-20
-30 100K
1M
10M
100M
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 5. FREQUENCY RESPONSE FOR VARIOUS CL
FIGURE 6. FREQUENCY RESPONSE FOR VARIOUS RL
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FN7176.1 November 19, 2004
EL5123, EL5223, EL5323, EL5423 Typical Performance Curves
100 PSRR+ 80 PSRR (dB) PSRROUTPUT IMPEDANCE () 480 600 VS=5V TA=25C
60
360
40
240
20 VS=5V 0 1K 10K
120
100K FREQUENCY (Hz)
1M
10M
0 100K
1M
10M
100M
FREQUENCY (Hz)
FIGURE 7. PSRR vs FREQUENCY
FIGURE 8. OUTPUT IMPEDANCE vs FREQUENCY
25
VOLTAGE NOISE (nV/Hz)
100 20 % OF BUFFERS
15
10
10
5
-6
-4
-2
1 10K
100K
1M FREQUENCY (Hz)
10M
100M
0 0 2 4 INPUT OFFSET VOLTAGE (mV) 6 85
FIGURE 9. INPUT NOISE SPECTRAL DENSITY vs FREQUENCY
2.5 INPUT BIAS CURRENT (nA)
FIGURE 10. INPUT OFFSET VOLTAGE DISTRIBUTION
4.955 OUTPUT HIGH VOLTAGE (V) 4.95 4.945 4.94 4.935 4.93 4.925
VS=5V
1.5
0.5
-0.5
-1.5
-2.5
VS=5V IOUT=5mA -35 -15 5 25 45 65
-35
-15
5
25
45
65
85
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 11. INPUT BIAS CURRENT vs TEMPERATURE
FIGURE 12. OUTPUT HIGH VOLTAGE vs TEMPERATURE
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FN7176.1 November 19, 2004
EL5123, EL5223, EL5323, EL5423 Typical Performance Curves
15.1 VS=5V OUTPUT LOW VOLTAGE (V) -4.934 VS=5V IOUT=-5mA
14.9 SLEW RATE (V/s)
-4.938
14.7
-4.942
14.5
-4.946
14.3
-4.95
14.1
-35
-15
5
25
45
65
85
-4.954
-35
-15
5
25
45
65
85
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 13. SLEW RATE vs TEMPERATURE
1.0014
FIGURE 14. OUTPUT LOW VOLTAGE vs TEMPERATURE
0.66
VS=5V SUPPLY CURRENT (mA)
VS=5V
VOLTAGE GAIN (V/V)
1.001
0.65
1.0006
0.64
1
0.63
0.9998 -35 -15 5 25 45 65 85 TEMPERATURE (C)
0.62
-35
-15
5
25
45
65
85
TEMPERATURE (C)
FIGURE 15. VOLTAGE GAIN vs TEMPERATURE
FIGURE 16. SUPPLY CURRENT PER CHANNEL vs TEMPERATURE
0.71
TA=25C
SUPPLY CURRENT (mA)
0.69
VS=5V RL=10k CL=12pF
0.67
50mV/DIV
0.65
0.63
4
6
8
10
12
14
16
18
200ns/DIV
SUPPLY VOLTAGE (V)
FIGURE 17. SUPPLY CURRENT PER CHANNEL vs SUPPLY VOLTAGE
FIGURE 18. SMALL SIGNAL TRANSIENT RESPONSE
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FN7176.1 November 19, 2004
EL5123, EL5223, EL5323, EL5423 Typical Performance Curves
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD, QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 2.857W
3 POWER DISSIPATION (W)
2.5 2.703W 2 1.5 1 0.5 0 QFN24 JA=37C/W QFN32 JA=35C/W
1V/DIV
1s/DIV
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
FIGURE 19. LARGE SIGNAL TRANSIENT RESPONSE
FIGURE 20. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.333W 1.176W 1.111W TSSOP24 JA=85C/W TSSOP28 JA=75C/W
0.8 0.7 POWER DISSIPATION (W) 0.6 0.5 0.4 0.3 0.2 0.1 0
JEDEC JESD51-3 AND SEMI G42-88 (SINGLE LAYER) TEST BOARD 758mW POWER DISSIPATION (W) 714mW QFN32 JA=132C/W
1.4 1.2 1
QFN24 JA=140C/W
0.8 870mW 0.6 0.4 0.2 0 0 25 TSSOP20 JA=95C/W MSOP10 JA=115C/W 50
0
25
50
75 85 100
125
150
75 85 100
125
150
AMBIENT TEMPERATURE (C)
AMBIENT TEMPERATURE (C)
FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 833mW 781mW 714mW TSSOP24 JA=128C/W TSSOP28 JA=120C/W
FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
0.9 0.8 POWER DISSIPATION (W) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
486mW MSOP10 JA=206C/W TSSOP20 JA=140C/W 0 25 50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
FIGURE 23. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
10
FN7176.1 November 19, 2004
EL5123, EL5223, EL5323, EL5423 Applications Information
Product Description
The EL5123, EL5223, EL5323, and EL5423 unity gain buffers are fabricated using a high voltage CMOS process. It exhibits rail-to-rail input and output capability and has low power consumption (600A per buffer). These features make the EL5123, EL5223, EL5323, and EL5423 ideal for a wide range of general-purpose applications. When driving a load of 10k and 12pF, the EL5123, EL5223, EL5323, and EL5423 have a -3dB bandwidth of 12MHz and exhibits 15V/s slew rate. exceeds 30mA. This limit is set by the design of the internal metal interconnects.
Output Phase Reversal
The EL5123, EL5223, EL5323, and EL5423 are immune to phase reversal as long as the input voltage is limited from VS- -0.5V to VS+ +0.5V. Figure 25 shows a photo of the output of the device with the input voltage driven beyond the supply rails. Although the device's output will not change phase, the input's over-voltage should be avoided. If an input voltage exceeds supply voltage by more than 0.6V, electrostatic protection diodes placed in the input stage of the device begin to conduct and over-voltage damage could occur.
1V 10s
Operating Voltage, Input, and Output
The EL5123, EL5223, EL5323, and EL5423 are specified with a single nominal supply voltage from 5V to 15V or a split supply with its total range from 5V to 15V. Correct operation is guaranteed for a supply range of 4.5V to 16.5V. Most EL5123, EL5223, EL5323, and EL5423 specifications are stable over both the full supply range and operating temperatures of -40C to +85C. Parameter variations with operating voltage and/or temperature are shown in the typical performance curves. The output swings of the EL5123, EL5223, EL5323, and EL5423 typically extend to within 50mV of positive and negative supply rails with load currents of 5mA. Decreasing load currents will extend the output voltage range even closer to the supply rails. Figure 24shows the input and output waveforms for the device. Operation is from 5V supply with a 10k load connected to GND. The input is a 10VP-P sinusoid. The output voltage is approximately 9.985VP-P.
5V 10s VS=5V TA=25C VIN=10VP-P
1V
VS=2.5V TA=25C VIN=6VP-P
FIGURE 25. OPERATION WITH BEYOND-THE-RAILS INPUT
Power Dissipation
With the high-output drive capability of the EL5123, EL5223, EL5323, and EL5423 buffer, it is possible to exceed the 125C "absolute-maximum junction temperature" under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the buffer to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to:
T JMAX - T AMAX P DMAX = -------------------------------------------d JA
OUTPUT
INPUT
5V
where: TJMAX = Maximum junction temperature
FIGURE 24. OPERATION WITH RAIL-TO-RAIL INPUT AND OUTPUT
TAMAX = Maximum ambient temperature JA = Thermal resistance of the package PDMAX = Maximum power dissipation in the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the loads, or:
P DMAX = i [ V S x I SMAX + ( V S + - V OUT i ) x I LOAD i ]
Short Circuit Current Limit
The EL5123, EL5223, EL5323, and EL5423 will limit the short circuit current to 120mA if the output is directly shorted to the positive or the negative supply. If an output is shorted indefinitely, the power dissipation could easily increase such that the device may be damaged. Maximum reliability is maintained if the output continuous current never
11
FN7176.1 November 19, 2004
EL5123, EL5223, EL5323, EL5423
when sourcing, and
P DMAX = i [ V S x I SMAX + ( V OUT i - V S - ) x I LOAD i ]
Power Supply Bypassing and Printed Circuit Board Layout
As with any high frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, lead lengths should be as short as possible, and the power supply pins must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to ground, a 0.1F ceramic capacitor should be placed from VS+ pin to ground. A 4.7F tantalum capacitor should then be connected from VS+ pin to ground. One 4.7F capacitor may be used for multiple devices. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used.
when sinking. where: i = 1 to Total number of buffers VS = Total supply voltage ISMAX = Maximum quiescent current per channel VOUTi = Maximum output voltage of the application ILOADi = Load current If we set the two PDMAX equations equal to each other, we can solve for RLOADi to avoid device overheat. The package power dissipation curves provide a convenient way to see if the device will overheat. The maximum safe power dissipation can be found graphically, based on the package type and the ambient temperature. By using the previous equation, it is a simple matter to see if PDMAX exceeds the device's power derating curves.
Unused Buffers
It is recommended that any unused buffer have the input tied to the ground plane.
Driving Capacitive Loads
The EL5123, EL5223, EL5323, and EL5423 can drive a wide range of capacitive loads. As load capacitance increases, however, the -3dB bandwidth of the device will decrease and the peaking increase. The buffers drive 10pF loads in parallel with 10k with just 1.5dB of peaking, and 100pF with 6.4dB of peaking. If less peaking is desired in these applications, a small series resistor (usually between 5 and 50) can be placed in series with the output. However, this will obviously reduce the gain slightly. Another method of reducing peaking is to add a "snubber" circuit at the output. A snubber is a shunt load consisting of a resistor in series with a capacitor. Values of 150 and 10nF are typical. The advantage of a snubber is that it does not draw any DC load current or reduce the gain.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN7176.1 November 19, 2004

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Price & Availability of EL5223

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